The present invention relates to the deposition of dielectric layers during wafer processing and more specifically to a method and apparatus for forming halogen-doped layers having a low dielectric constant and high film stability.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition or "CVD". Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having metal layers. Plasma enhanced CVD (frequently referred to as PECVD) processes on the other hand, promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone proximate the substrate surface, thereby creating a plasma of highly-reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such CVD processes. The relatively low temperature of a PECVD process makes such processes ideal for the formation of insulating layers over deposited metal layers.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called "Moore's Law") which means that the number of devices which will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing 0.5 and even 0.35 micron feature size devices, and tomorrow's plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, issues which were not previously considered important by the industry are becoming of paramount concern. With the advent of multilevel metal technology in which three, four, or more layers of metal are formed on the semiconductors, one goal of semiconductor manufacturers is lowering the dielectric constant of insulating layers such as intermetal dielectric layers deposited by PECVD methods. Low dielectric constant films are particularly desirable for intermetal dielectric (IMD) layers to reduce the RC time delay of the interconnect metallization, to prevent cross-talk between the different levels of metallization, and to reduce device power consumption.
Many approaches to obtain lower dielectric constants have been proposed. One of the more promising solutions is the incorporation of fluorine or other halogen elements, such as chlorine or bromine into a silicon oxide layer. An example of halogen incorporation is described in U.S. Ser. No. 08/344,283 commonly assigned to Applied Materials, Inc. filed on Nov. 24, 1994 and incorporated herein by reference. Fluorine, the preferred halogen dopant for silicon oxide films, lowers the dielectric constant of the silicon oxide film because fluorine is an electronegative atom that decreases the polarizability of the overall SiOF network. Fluorine-doped silicon oxide films are also referred to as fluoro silicate glass films or FSG for short.
In addition to decreasing the dielectric constant, incorporating fluorine in intermetal silicon oxide layers also helps solve common problems encountered in fabricating smaller geometry devices, such as filling closely spaced gaps on semiconductor structures. It is believed that because fluorine is an etching species, fluorine doping introduces a deposition/etch/deposition effect on oxide formation. The deposition/etch/deposition effect allows FSG films to have improved gap filling capabilities such that the films are able to adequately cover adjacent metal layers having an aspect ratio of 1.8 or more.
Thus, manufacturers desire to include fluorine in various dielectric layers and particularly in intermetal dielectric layers. A problem with the incorporation of fluorine in silicon oxide or similar films, however, has been keeping the fluorine in the film. Experiments have shown only a certain level of fluorine is retained in a silicon oxide layer, even when the gas flow of the fluorine containing source gas is increased during the CVD process.
At least two separate forces effect the fluorine retention rate. The first is that FSG films absorb moisture easily. Clean rooms have a ambient moisture in the air. When a wafer is exposed to the ambient in a clean room, for example, when the wafer is passed to a new processing chamber after deposition of the oxide layer, the FSG layer absorbs moisture, thus increasing the film's dielectric constant. The absorbed moisture (H.sub.2 O) also reacts with the fluorine to form hydrofluoric acid (HF).
Another problem with FSG films occurs when the film is exposed to a thermal process such as an anneal process. The high temperature of the thermal processes can move the fluorine atoms out of the oxide layer through metal or other subsequently deposited layers. The excursion of fluorine atoms in this manner is referred to as outgassing.
From the above, it can be seen that an oxide film having a low dielectric constant is necessary to keep pace with emerging technologies. It can also be seen that a method is needed to prevent moisture absorption and outgassing in fluorine-doped oxide films.